There are four system console control panels designed for this hardware demo with straight forward hardware status monitoring and simple mouse click operation.Īs mentioned in previous sections, the 40G Ethernet sub-system consists of 40G MAC and PHY sub-modules. This hardware demo design use System Console to run TCL script which is platform independent, can run on a PC (windows based operating system) or any Linux Machine. The traffic monitor is able to check packet sequence number, packet length. The packet payload be configured as either incremental or configurable fixed. This traffic generator can be operated in two modes: continuous mode and burst mode. The traffic generator is able to generate fixed size packets with length from 33-byte to 32768-byte. Monitor parses all packets received from MAC and checks the integrity of the packets. The generator can generate random packets. There is also a 32-bit Avalon-MM configuration and status interface associated with both the generator and the monitor. These modules have 256-bit Avalon-ST interface for the data-path and connect to the 40G Ethernet MAC. The Packet Client includes a Packet Generator and a simple Packet Monitor. Packet Client with Random Size Packet Generator and Monitor Similarly, in the RX direction, the MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. In the TX direction, the MAC accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header, padding, and checksum before passing them to the PHY. This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 40GbE Ethernet PCS and PMA (PHY). The Altera 40G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 803.3ba 2010 Higher Speed Ethernet Standard. The following diagram can represent this system: System console GUI for configuration and control of the system.Packet Client with random and fixed size packet Generator and Monitor.System Overview The hardware platform consists of three sub-systems: System console GUI based flexible, reusable, and extendable user control interface allows users to dynamically configure and monitor any configuration registers provided by this demo design.Provides both random and fixed size packet generator.Uses a standard 256-bit Avalon-ST interface to connect to the Ethernet Packet Generator and Monitor.Stand-alone and easy-to-use design example with flexibility to dynamically select traffic profile.This hardware demonstration reference design offers the following features: This design provides a flexible test and demonstration platform which effectively control, test, and monitor 40Gbps Ethernet packets using internal serial PMA loopback and external optical loopback, MAC client side RX to TX parallel loopback. It is configured to demonstrate on a Stratix V GX FPGA Development Kit, also called PCIe Dev Kit using Altera development tool Quartus II 15.0 production release. This hardware demo design demonstrates the operation of Altera® 40-Gbps Ethernet MAC and PHY IP solution on a Stratix V device (5SGXEA7K2F40C2N). 40Gbps Ethernet MACPHY IP Hardware Demo Design using QSFPĤ0Gbps Ethernet MAC PHY IP Hardware Demo Design using QSFP Introduction
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